1. Field of Invention
The present invention relates to a method of fabricating integrated circuits (IC). More particularly, the present invention relates to a method of fabricating a metal-oxide-semiconductor (MOS) device.
2. Description of Related Art
The conventional method of fabricating the MOS device is to form a gate oxide layer and a polysilicon gate on the substrate. The polysilicon gate is used as the implantation mask, while dopants are implanted in the substrate by ion implantation to form the source/drain extension. After spacers are formed on sidewalls of the polysilicon gate, dopants are ion-implanted in the substrate to form the source/drain while using the polysilicon gate and spacers as the implantation mask. Afterwards, a high temperature annealing process is used to activate dopants in the source/drain extension and the source/drain. Lastly, a dielectric layer is formed over the substrate for further metal interconnects process.
In order to be compatible with the market requirement for the minimum device size, the semiconductor devices are manufactured with high integration at the present. The conventional method for increasing gate capacitance of the MOS device is to decrease the thickness of the gate oxide layer. However, it is not possible to keep decreasing the thickness of the gate oxide layer, especially when IC manufacture is moving into the sub micron processes. When the thickness of the oxide layer decreases to a certain level, the defects in the oxide layer cause current leakage of the device and reduction of drain current, and may even lead to severe short channel effect.
On the other hand, polysilicon or polycide material is used to form the gate layer in the conventional MOS device. In general, dopants are implanted in the polysilicon to increase its conductivity and reduce its resistivity. However, the dopant concentration is pretty limited in the polysilicon, which causes restricted resistivity reduction and further influences the speed as well as operation performance. Moreover, a depletion region is formed during the operation and a depletion capacitor is induced in this MOS device made of polysilicon or polycide material, causing capacitance of the whole transistor to decrease.
In addition, the boron atoms implanted during the ion implantation process of the source/drain extension and the source/drain might inject along the polysilicon lattice and penetrate the gate oxide layer. This raises problems in the electrical properties of the device. Furthermore, the high temperature armealing process performed after the ion implantation process of the source/drain extension and the source/drain causes changes in the implantation profile and results in a deeper junction depth than desired.